Laptop computers, personal digital assistants (PDAs), cell phones and other portable equipment often use additional battery packs to extend equipment “on” and “standby” times. Management of charge flow between the battery pack, load, external charger and additional add on battery packs often require sophisticated battery management circuitry. An example of such a circuit is shown in U.S. Pat. No. 5,764,032 to Moore.
FIG. 1 shows a circuit similar to the one shown by U.S. Pat. No. 5,764,032. The circuit shown by FIG. 1 contains 6 P-channel power MOSFETs Q1,Q2,Q3,Q4,Q5,Q6. Power MOSFETs Q1,Q2,Q3,Q4,Q5,Q6 are all driven by control IC 20. That is, control IC 20 provides signals to the gate of each of the power MOSFETs Q1,Q2,Q3,Q4,Q5,Q6 in order to cause each to conduct electricity.
The circuit of FIG. 1 is symmetric and can be understood by considering one side only. Specifically, low side MOSFET Q1 works in conjunction with MOSFET Q2 as a charge control device, limiting the flow of charge from the charge input to battery A when overcharge conditions are detected by control IC 20. MOSFET Q2 prevents charge flowing from battery B into battery A. MOSFET Q1 is a discharge control device that, when required, limits current flow between battery A and the load. This may occur during load short circuit conditions, or when the battery minimum cut-off voltage has been detected.
A circuit such as the one shown by FIG. 1 would require three discreet MOSFETs, which are connected in a common drain fashion. Such a configuration results in losses, which is undesirable particularly in portable, battery operated devices in which efficiency is an important parameter.